1. Field of the Invention
The disclosed technology generally relates to packaging of semiconductor components, such as integrated circuit chips, and more in particular to packaging of semiconductor components using pillar-type microbumps.
2. Description of the Related Technology
In systems for high performance applications such as Memory-Logic or Logic-Serializer/Deserializer (SERDES), the packaging technology chosen to interface the semiconductor chips can have a significant impact on the performance of the overall system. Generally, the bandwidth of the interconnections can be improved by increasing the number of Input/Output (I/O) between the chips. To increase the number of I/O in flip-chip/3D packaging technologies, the number of microbumps to interface the chips may correspondingly be increased, for example, by decreasing pitch and dimensions of the microbumps. Pillar-type microbumps (in contrast to solder ball-type) are typically used for forming microbumps having a pitch of 40-50 μm or less. For forming microbumps having smaller pitches (e.g., 20 μm or below), the underlying structures and/or the bump adhesion (affected by the bump diameter reduction) can introduce undesirable topographies on surfaces of the microbumps, which can hinder stacking and cause yield loss and/or reliability degradation. Thus, there is a need to minimize undesirable topographies on surfaces of microbumps that may result due to similar topography that may be present in the underlying structures, such as contact openings.